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IDTTM InterpriseTM Integrated Communications Processor
79RC32351
Features List
RC32300 32-bit Microprocessor - Enhanced MIPS-II ISA - Enhanced MIPS-IV cache prefetch instruction - DSP Instructions - MMU with 16-entry TLB - 8kB Instruction cache, 2-way set associative - 2kB Data cache, 2-way set associative - Per line cache locking - Write-through and write-back cache management - Debug interface through the EJTAG port - Big or little endian support Interrupt Controller - Allows status of each interrupt to be read and masked UARTs - Two 16550 Compatible UARTs - Baud rate support up to 1.5 Mb/s Counter/Timers - Three general purpose 32-bit counter/timers General Purpose I/O Pins (GPIOP) - 32 individually programmable pins: each pin programmable as input, output, or alternate function, input can be an interrupt or NMI source, input can also be active high or active low - 4 additional, auxiliary GPIO pins can be configured as input or output
SDRAM Controller - 2 memory banks, non-interleaved, 512 MB total - 32-bit wide data path - Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips - SODIMM support - Stays on page between transfers - Automatic refresh generation Peripheral Device Controller - 26-bit address bus - 32-bit data bus with variable width support of 8-,16-, or 32-bits - 8-bit boot ROM support - 6 banks available, up to 64MB per bank - Supports Flash ROM, PROM, SRAM, dual-port memory, and peripheral devices - Supports external wait-state generation, Intel or Motorola style - Write protect capability - Direct control of optional external data transceivers System Integrity - Programmable system watchdog timer resets system on timeout - Programmable bus transaction times memory and peripheral transactions and generates a warm reset on time-out DMA - 14 DMA channels - Services on-chip and external peripherals - Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O transfers - Supports flexible descriptor based operation and chaining via linked lists of records (scatter / gather capability) - Supports unaligned transfers
Block Diagram
RC32300 CPU Core ICE
EJTAG MMU I. Cache Interrupt Controller : : Watchdog Timer
10/100 Ethernet Interface
USB Interface 16 Channel DMA Controller Arbiter
D. Cache
3 Counter Timers
Ext. Bus Master
SDRAM & Device Controller
2 UARTS
(16550)
GPIO Interface
ATM Interface
Memory & Peripheral Bus
Ch. 1 Ch. 2 Serial Channels
GPIO Pins
Utopia 1 / 2
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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(c) 2002 Integrated Device Technology, Inc.
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DSC 6053
IDT 79RC32351
- Supports burst transfers USB - Revision 1.1 compliant - USB slave device controller - Supports a 6th USB endpoint - Full speed operation at 12 Mb/s - Supports control, interrupt, bulk and isochronous endpoints - Supports USB remote wakeup - Integrated USB transceiver EJTAG - Run-time Mode provides a standard JTAG interface - Real-Time Mode provides additional pins for real-time trace information Ethernet - Full duplex support for 10 and 100 Mb/s Ethernet - IEEE 802.3u compatible Media Independent Interface (MII) with serial management interface - IEEE 802.3u auto-negotiation for automatic speed selection - Flexible address filtering modes - 64-entry hash table based multicast address filtering
ATM SAR - Can be configured as one UTOPIA level 1 interface or 1 UTOPIA level 2 interface with 2 address lines (3 PHYs max) - Supports 25Mb/s and faster ATM - Supports UTOPIA data path interface operation at speeds up to 33 MHz - Supports standard 53-byte ATM cells - Performs HEC generation and checking - Cell processing discards short cells and clips long cells - 16 cells worth of buffering - UTOPIA modes: 8 cell input buffer and 8 cell output buffer - Hardware support for CRC-32 generation and checking for AAL5 - Hardware support for CRC-10 generation and checking - Virtual caching receive mechanism supports reception of any length packet without CPU intervention on up to eight simultaneously active receive channels - Frame Mode transmit mechanism supports transmission of any length packet without CPU intervention System Features - JTAG interface (IEEE Std. 1149.1 compatible) - 208 pin PQFP package - 2.5V core supply and 3.3V I/O supply - Up to 133 MHz pipeline frequency and up to 66 MHz bus frequency
RC32300 CPU Core Debug port Timers UART Interrupt Ctl DMA Channels USB to PC USB Data Buffers SDRAM Ctl Memory & I/O Controller ATM I/F Ethernet MAC MII I/F Ethernet Transceiver Ethernet to PC
Clock 32-bit Data Bus
SDRAM Memory & I/O Transmission Convergence
Data Pump AFE
Figure 2 Example of xDSL Residential Gateway Using RC32351 2 of 42 May 25, 2004
IDT 79RC32351
Device Overview
The RC32351 is a "System on a Chip" which contains a high performance 32-bit microprocessor. The microprocessor core is used extensively at the heart of the device to implement the most needed functionalities in software with minimal hardware support. The high performance microprocessor handles diverse general computing tasks and specific application tasks that would have required dedicated hardware. Specific application tasks implemented in software can include routing functions, fire wall functions, modem emulation, ATM SAR emulation, and others. The RC32351 meets the requirements of various embedded communications and digital consumer applications. It is a single chip solution that incorporates most of the generic system functionalities and application specific interfaces that enable rapid time to market, very low cost systems, simplified designs, and reduced board real estate. CPU Execution Core The RC32351 is built around the RC32300 32-bit high performance microprocessor core. The RC32300 implements the enhanced MIPS-II ISA and helps meet the real-time goals and maximize throughput of communications and consumer systems by providing capabilities such as a prefetch instruction, multiple DSP instructions, and cache locking. The DSP instructions enable the RC32300 to implement 33.6 and 56kbps modem functionality in software, removing the need for external dedicated hardware. Cache locking guarantees real-time performance by holding critical DSP code and parameters in the cache for immediate availability. The microprocessor also implements an on-chip MMU with a TLB, making the it fully compliant with the requirements of real time operating systems. Memory and IO Controller The RC32351 incorporates a flexible memory and peripheral device controller providing support for SDRAM, Flash ROM, SRAM, dual-port memory, and other I/O devices. It can interface directly to 8-bit boot ROM for a very low cost system implementation. It enables access to high bandwidth external memory (200 MB/sec peak) at very low system costs. It also offers various trade-offs in cost / performance for the main memory architecture. The timers implemented on the RC32351 satisfy the requirements of most RTOS.
DMA Controller The DMA controller off-loads the CPU core from moving data among the on-chip interfaces, external peripherals, and memory. The DMA controller supports scatter / gather DMA with no alignment restrictions, appropriate for communications and graphics systems. Ethernet Interface The RC32351 contains an on-chip Ethernet MAC capable of 10 and 100 Mbps line interface with an MII interface. It supports up to 4 MAC addresses. In a SOHO router, the high performance RC32300 CPU core routes the data between the Ethernet and the ATM interface. In other applications, such as high speed modems, the Ethernet interface can be used to connect to the PC. USB Device Interface The RC32351 includes the industry standard USB device interface to enable consumer appliances to directly connect to the PC. ATM SAR The RC32351 includes a configurable ATM SAR that supports a UTOPIA level 1 or a UTOPIA level 2 interface. The ATM SAR is implemented as a hybrid between software and hardware. A hardware block provides the necessary low level blocks (like CRC generation and checking and cell buffering) while the software is used for higher level SARing functions. In xDSL modem applications, the UTOPIA port interfaces directly to an xDSL chip set. In SOHO routers or in a line card for a Layer 3 switch, it provides access to an ATM network. Enhanced JTAG Interface for ICE For low-cost In-Circuit Emulation (ICE), the RC32300 CPU core includes an Enhanced JTAG (EJTAG) interface. This interface consists of two operation modes: Run-Time Mode and Real-Time Mode. The Run-Time Mode provides a standard JTAG interface for on-chip debugging, and the Real-Time Mode provides additional status pins-- PCST[2:0]--which are used in conjunction with the JTAG pins for realtime trace information at the processor internal clock or any division of the pipeline clock.
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IDT 79RC32351
Thermal Considerations
The RC32351 consumes less than 1.5 W peak power and is guaranteed in an ambient temperature range of 0 to +70 C (commercial).
Revision History
January 7, 2002: Initial publication. May 20, 2002: Added values (in place of TBD) to Table 18, Power Consumption. September 19, 2002: Added COLDRSTN Trise1 parameter to Table 5, Reset and System AC Timing Characteristics. December 6, 2002: In Features section, changed UART speed from 115 Kb/s to 1.5 Mb/s. December 17, 2002: Added VOH parameter to Table 16, DC Electrical Characteristics. May 25, 2004: In Table 7, signals MIIRXCLK and MIITXCLK, the Min and Max values for 10 Mbps Thigh1/Tlow1 were changed to 140 and 260 respectively and the Min and Max values for 100 Mbps Thigh1/ Tlow1 were changed to 14.0 and 26.0 respectively.
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IDT 79RC32351
Pin Description Table
The following table lists the functions of the pins provided on the RC32351. Some of the functions listed may be multiplexed onto the same pin. To define the active polarity of a signal, a suffix will be used. Signals ending with an "N" should be interpreted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. Note: The input pads of the RC32351 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32351's operation. Also, any input pin left floating can cause a slight increase in power consumption.
Name System CLKP COLDRSTN RSTN I I I/O Input STI1 System Clock input. This is the system master clock input. The RISCore 32300 pipeline frequency is a multiple (x2, x3, or x4) of this clock frequency. All other logic runs at this frequency or less. Cold Reset. The assertion of this signal low initiates a cold reset. This causes the RC32351 state to be initialized, boot configuration to be loaded, and the internal processor PLL to lock onto the system clock (CLKP). Type I/O Type Description
Low Drive Reset. This bidirectional signal is either driven low or tri-stated, an external pull-up is required to supply the high state. The with STI RC32351 drives RSTN low during a reset (to inform the external system that a reset is taking place) and then tri-states it. The external system can drive RSTN low to initiate a warm reset, and then should tri-state it. High Drive System clock output. This is a buffered and delayed version of the system clock input (CLKP). All SDRAM transactions are synchronous to this clock. This pin should be externally connected to the SDRAMs and to the RC32351 SDCLKINP pin (SDRAM clock input). [21:0] High Memory Address Bus. 26-bit address bus for memory and peripheral accesses. MADDR[20:17] are used for the SODIMM data mask enables if SODIMM mode is selected. Drive [25:22] Low MADDR[22] Primary function: General Purpose I/O, GPIOP[27]. Drive with MADDR[23] Primary function: General Purpose I/O, GPIOP[28]. MADDR[24] Primary function: General Purpose I/O, GPIOP[29]. STI MADDR[25] Primary function: General Purpose I/O, GPIOP[30].
SYSCLKP
O
Memory and Peripheral Bus MADDR[25:0] O
MDATA[31:0] BDIRN BOEN[1:0]
I/O O O
High Drive Memory Data Bus. 32-bit data bus for memory and peripheral accesses. High Drive External Buffer Direction. External transceiver direction control for the memory and peripheral data bus, MDATA[31:0]. It is asserted low during any read transaction, and remains high during write transactions. High Drive External Buffer Output Enable. These signals provide two output enable controls for external data bus transceivers on the memory and peripheral data bus, MDATA. BOEN[0] is asserted low during external device read transactions. BOEN[1] is asserted low during SDRAM read transactions. STI External Bus Request. This signal is asserted low by an external master device to request ownership of the memory and peripheral bus.
BRN BGN WAITACKN
I O I
Low Drive External Bus Grant. This signal is asserted low by RC32351 to indicate that RC32351 has relinquished ownership of the local memory and peripheral bus to an external master. STI Wait or Transfer Acknowledge. When configured as wait, this signal is asserted low during a memory and peripheral device bus transaction to extend the bus cycle. When configured as transfer acknowledge, this signal is asserted low during a memory and peripheral device bus transaction to signal the completion of the transaction.
CSN[5:0]
O
Device Chip Select. These signals are used to select an external device on the memory and peripheral bus during device [3:0] High Drive transactions. Each bit is asserted low during an access to the selected external device. CSN[4] Primary function: General purpose I/O, GPIOP[16]. [5:4] CSN[5] Primary function: General purpose I/O, GPIOP[17]. Low Drive Table 1 Pin Descriptions (Part 1 of 7)
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IDT 79RC32351 Name RWN OEN BWEN[3:0] Type I/O Type O O O Description
High Drive Read or Write. This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write transaction. A high level indicates a read from an external device, a low level indicates a write to an external device. High Drive Output Enable. This signal is asserted low when data should be driven by an external device during device read transactions on the memory and peripheral bus. High Drive SDRAM Byte Enable Mask or Memory and I/O Byte Write Enables. These signals are used as data input/output masks during SDRAM transactions and as byte write enable signals during device controller transactions on the memory and peripheral bus. They are active low. BWEN[0] corresponds to byte lane MDATA[7:0]. BWEN[1] corresponds to byte lane MDATA[15:8]. BWEN[2] corresponds to byte lane MDATA[23:16]. BWEN[3] corresponds to byte lane MDATA[31:24]. High Drive SDRAM Chip Select. These signals are used to select the SDRAM device on the memory and peripheral bus. Each bit is asserted low during an access to the selected SDRAM. High Drive SDRAM Row Address Strobe. The row address strobe asserted low during memory and peripheral bus SDRAM transactions. High Drive SDRAM Column Address Strobe. The column address strobe asserted low during memory and peripheral bus SDRAM transactions. High Drive SDRAM Write Enable. Asserted low during memory and peripheral bus SDRAM write transactions. Low Drive SDRAM Clock Enable. Asserted high during active SDRAM clock cycles. Primary function: General Purpose I/O, GPIOP[21]. STI SDRAM Clock Input. This clock input is a delayed version of SYSCLKP. SDRAM read data is sampled into the RC32351 on the rising edge of this clock. ATM PHY Inputs. These pins are the inputs for the ATM interface.
SDCSN[1:0] RASN CASN SDWEN CKENP SDCLKINP ATM Interface ATMINP[11:0] ATMIOP[1:0] ATMOUTP[9:0] TXADDR[1:0]
O O O O O I
I I/O O O
STI
Low Drive ATM PHY Bidirectional Signals. These pins are the bidirectional pins for the ATM interface. with STI Low Drive ATM PHY Outputs. These pins are the outputs for the ATM interface. Low Drive ATM Transmit Address [1:0]. 2-bit address bus used for transmission in Utopia-2 mode. TXADDR[0] Primary function: General purpose I/O, GPIOP[22]. TXADDR[1] Primary function: General purpose I/O, GPIOP[23]. Low Drive ATM Receive Address [1:0]. 2-bit address bus for receiving in Utopia-2 mode. RXADDR[0] Primary function: General purpose I/O, GPIOP[24]. RXADDR[1] Primary function: General purpose I/O, GPIOP[25]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: UART channel 0 serial output, U0SOUTP. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: UART channel 0 serial input, U0SINP. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: UART channel 0 ring indicator, U0RIN. 2nd Alternate function: JTAG boundary scan tap controller reset, JTAG_TRST_N. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: UART channel 0 data carrier detect, U0DCRN. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: UART channel 0 data terminal ready, U0DTRN. 2nd Alternate function: CPU or DMA transaction indicator, CPUP. Table 1 Pin Descriptions (Part 2 of 7)
RXADDR[1:0]
O
General Purpose Input/Output GPIOP[0] GPIOP[1] GPIOP[2] I/O I/O I/O
GPIOP[3] GPIOP[4]
I/O I/O
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IDT 79RC32351 Name GPIOP[5] GPIOP[6] GPIOP[7] Type I/O Type I/O I/O I/O Description
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: UART channel 0 data set ready, U0DSRN. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: UART channel 0 request to send, U0RTSN. Low Drive General Purpose I/O. with STI This pin can be configured as a general purpose I/O pin. Alternate function: UART channel 0 clear to send, U0CTSN. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: UART channel 1 serial output, U1SOUTP. 2nd Alternate function: Active DMA channel code, DMAP[3]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: UART channel 1 serial input, U1SINP. 2nd Alternate function: Active DMA channel code, DMAP[2]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: UART channel 1 data terminal ready, U1DTRN. 2nd Alternate function: ICE PC trace status, EJTAG_PCST[0]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: UART channel 1 data set ready, U1DSRN. 2nd Alternate function: ICE PC trace status, EJTAG_PCST[1]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: UART channel 1 request to send, U1RTSN. 2nd Alternate function: ICE PC trace status, EJTAG_PCST[2]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: UART channel 1 clear to send, U1CTSN. 2nd Alternate function: ICE PC trace clock, EJTAG_DCLK. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI High Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function: Memory and peripheral bus chip select, CSN[4]. High Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function: Memory and peripheral bus chip select, CSN[5]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: External DMA device request, DMAREQN. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: External DMA device done, DMADONEN. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: USB start of frame, USBSOF. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: SDRAM clock enable CKENP. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: ATM transmit PHY address, TXADDR[0]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: ATM transmit PHY address, TXADDR[1]. 2nd Alternate function: Active DMA channel code, DMAP[0]. Table 1 Pin Descriptions (Part 3 of 7)
GPIOP[8]
I/O
GPIOP[9]
I/O
GPIOP[10]
I/O
GPIOP[11]
I/O
GPIOP[12]
I/O
GPIOP[13]
I/O
GPIOP[14] GPIOP[15] GPIOP[16] GPIOP[17] GPIOP[18] GPIOP[19] GPIOP[20] GPIOP[21] GPIOP[22] GPIOP[23]
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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IDT 79RC32351 Name GPIOP[24] GPIOP[25] Type I/O Type I/O I/O Description
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: ATM receive PHY address, RXADDR[0]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1st Alternate function: ATM receive PHY address, RXADDR[1]. 2nd Alternate function: Active DMA channel code, DMAP[1]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: Memory and peripheral bus address, MADDR[22]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: Memory and peripheral bus address, MADDR[23]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: Memory and peripheral bus address, MADDR[24]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: Memory and peripheral bus address, MADDR[25]. Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI 1ST Alternate function: DMA finished, DMAFIN. 2nd Alternate function: EJTAG/ICE reset, EJTAG_TRST_N. High Drive General Purpose I/O. This pin can be configured as an auxiliary general purpose I/O pin. Low Drive General Purpose I/O. This pin can be configured as an auxiliary general purpose I/O pin. with STI High Drive General Purpose I/O. This pin can be configured as an auxiliary general purpose I/O pin. Low Drive General Purpose I/O. This pin can be configured as an auxiliary general purpose I/O pin. with STI Low External DMA finished. This signal is asserted low by the RC32351 when the number of bytes specified in the DMA descriptor have been transferred to or from an external device. Primary function: General Purpose I/O, GPIOP[31]. At reset, this pin defaults to primary function GPIOP[31]. 2nd Alternate function: EJTAG_TRST_N. External DMA Device Request. The external DMA device asserts this pin low to request DMA service. Primary function: General purpose I/O, GPIOP[18]. At reset, this pin defaults to primary function GPIOP[18]. External DMA Device Done. The external DMA device asserts this signal low to inform the RC32351 that it is done with the current DMA transaction. Primary function: General purpose I/O, GPIOP[19]. At reset, this pin defaults to primary function GPIOP[19]. USB Clock. 48 MHz clock input used as time base for the USB interface. USB D- Data Line. This is the negative differential USB data signal. USB D+ Data Line. This is the positive differential USB data signal.
GPIOP[26] GPIOP[27] GPIOP[28] GPIOP[29] GPIOP[30] GPIOP[31]
I/O I/O I/O I/O I/O I/O
GPIOP[32] GPIOP[33] GPIOP[34] GPIOP[35] DMA DMAFIN
I/O I/O I/O I/O
O
DMAREQN DMADONEN
I I
STI STI
USB USBCLKP USBDN USBDP USBSOF Ethernet MIICOLP MIICRSP MIIMDCP I I O STI STI MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected. MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle. I I/O I/O O STI USB USB
Low Drive USB start of frame. Primary function: General Purpose I/O, GPIOP[20]. At reset, this pin defaults to primary function GPIOP[20].
Low Drive MII Management Data Clock. This signal is used as a timing reference for transmission of data on the management interface. Table 1 Pin Descriptions (Part 4 of 7)
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IDT 79RC32351 Name MIIMDIOP MIIRXCLKP MIIRXDP[3:0] MIIRXDVP MIIRXERP MIITXCLKP MIITXDP[3:0] MIITXENP MIITXERP EJTAG JTAG_TCK JTAG_TDI I I STI STI JTAG Clock. This is an input test clock, used to shift data into or out of the boundary scan logic. This signal requires an external resistor, listed in Table 14. JTAG Data Input. This is the serial data shifted into the boundary scan logic. This signal requires an external resistor, listed in Table 14. This is also used to input EJTAG_DINTN during EJTAG/ICE mode. EJTAG_DINTN is an interrupt to switch the PC trace mode off. Type I/O Type I/O I I I I I O O O Description
Low Drive MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the with STI ethernet PHY. STI STI STI STI STI MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data. MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY. MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus. MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the MII receive data bus. MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data.
Low Drive MII Transmit Data. This nibble wide data bus contains the data to be transmitted. Low Drive MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission. Low Drive MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols which are not valid data or delimiters.
JTAG_TDO
O
Low Drive JTAG Data Output. This is the serial data shifted out from the boundary scan logic. When no data is being shifted out, this signal is tri-stated. This signal requires an external resistor, listed in Table 14. This is also used to output the EJTAG_TPC during EJTAG/ICE mode. EJTAG_TPC is the non-sequential program counter output. STI JTAG Mode Select. This input signal is decoded by the tap controller to control test operation. This signal requires an external resistor, listed in Table 14.
JTAG_TMS EJTAG_PCST[0]
I O
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires an external resistor, listed in Table 14. Primary function: General Purpose I/O, GPIOP[10]. 1st Alternate function: UART channel 1 data terminal ready, U1DTRN. Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires an external resistor, listed in Table 14. Primary function: General Purpose I/O, GPIOP[11]. At reset, this pin defaults to primary function GPIOP[11]. 1st Alternate function: UART channel 1 data set ready, U1DSRN. Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires an external resistor, listed in Table 14. Primary function: General Purpose I/O, GPIOP[12]. 1st Alternate function: UART channel 1 request to send, U1RTSN. Low Drive PC trace clock. This is used to capture address and data during EJTAG/ICE mode. EJTAG/ICE enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires an external resistor, listed in Table 14. Primary function: General Purpose I/O, GPIOP[13]. 1st Alternate function: UART channel 1 clear to send, U1CTSN. Table 1 Pin Descriptions (Part 5 of 7)
EJTAG_PCST[1]
O
EJTAG_PCST[2]
O
EJTAG_DCLK
O
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IDT 79RC32351 Name EJTAG_TRST_N Type I/O Type I STI Description EJTAG Test Reset. EJTAG_TRST_N is an active-low signal for asynchronous reset of only the EJTAG/ICE controller. EJTAG_TRST_N requires an external pull-up on the board. EJTAG/ICE enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires an external resistor, listed in Table 14. Primary: General Purpose I/O, GPIOP[31] 1st Alternate function: DMA finished output, DMAFIN. JTAG Test Reset. JTAG_TRST_N is an active-low signal for asynchronous reset of only the JTAG boundary scan controller. JTAG_TRST_N requires an external pull-down on the board that will hold the JTAG boundary scan controller in reset when not in use if selected. JTAG reset enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. Primary function: General Purpose I/O, GPIOP[2]. 1st Alternate function: UART channel 0 ring indicator, U0RIN.
JTAG_TRST_N
I
STI
Debug INSTP CPUP O O Low Drive Instruction or Data Indicator. This signal is driven high during CPU instruction fetches and low during CPU data transactions on the memory and peripheral bus. Low Drive CPU or DMA Transaction Indicator. This signal is driven high during CPU transactions and low during DMA transactions on the memory and peripheral bus if CPU/DMA Transaction Indicator Enable is enabled. CPU/DMA Status mode enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. Primary function: General Purpose I/O, GPIOP[4]. 1st Alternate function: UART channel 0 data terminal ready U0DTRN. Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. Primary function: General Purpose I/O, GPIOP[23]. 1st Alternate function: TXADDR[1]. Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. Primary function: General Purpose I/O, GPIOP[25]. 1st Alternate function: RXADDR[1]. Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. Primary function: General Purpose I/O, GPIOP[9]. 1st Alternate function: U1SINP. Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. Primary function: General Purpose I/O, GPIOP[8]. 1st Alternate function: U1SOUTP. STI STI STI UART channel 0 serial transmit. Primary function: General Purpose I/O, GPIOP[0]. At reset, this pin defaults to primary function GPIOP[0]. UART channel 0 serial receive. Primary function: General Purpose I/O, GPIOP[1]. At reset, this pin defaults to primary function GPIOP[1]. UART channel 0 ring indicator. Primary function: General Purpose I/O, GPIOP[2]. At reset, this pin defaults to primary function GPIOP[2] if JTAG reset enable is not selected during reset using the boot configuration. 2nd Alternate function: JTAG boundary scan reset, JTAG_TRST_N. UART channel 0 data carrier detect. Primary function: General Purpose I/O, GPIOP[3]. At reset, this pin defaults to primary function GPIOP[3]. Table 1 Pin Descriptions (Part 6 of 7)
DMAP[0]
O
DMAP[1]
O
DMAP[2]
O
DMAP[3]
O
UART U0SOUTP U0SINP U0RIN I I I
U0DCRN
I
STI
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May 25, 2004
IDT 79RC32351 Name U0DTRN Type I/O Type O Description
Low Drive UART channel 0 data terminal ready. Primary function: General Purpose I/O, GPIOP[4]. At reset, this pin defaults to primary function GPIOP[4] if CPU/DMA Status Mode enable is not selected during reset using the boot configuration. 2nd Alternate function: CPU or DMA transaction indicator, CPUP. STI UART channel 0 data set ready. Primary function: General Purpose I/O, GPIOP[5]. At reset, this pin defaults to primary function GPIOP[5].
U0DSRN U0RTSN U0CTSN U0SOUTP
I O I O
Low Drive UART channel 0 request to send. Primary function: General Purpose I/O, GPIOP[6]. At reset, this pin defaults to primary function GPIOP[6]. STI UART channel 0 clear to send. Primary function: General Purpose I/O, GPIOP[7]. At reset, this pin defaults to primary function GPIOP[7].
Low Drive UART channel 1 serial transmit. Primary function: General Purpose I/O, GPIOP[8]. At reset, this pin defaults to primary function GPIOP[8] if DMA Debug enable is not selected during reset using the boot configuration. 2nd Alternate function: DMA channel, DMAP[3]. STI UART channel 1 serial receive. Primary function: General Purpose I/O, GPIOP[9]. At reset, this pin defaults to primary function GPIOP[9] if DMA Debug enable is not selected during reset using the boot configuration. 2nd Alternate function: DMA channel, DMAP[2].
U1SINP
I
U1DTRN
O
Low Drive UART channel 1 data terminal ready. Primary function: General Purpose I/O, GPIOP[10]. At reset, this pin defaults to primary function GPIOP[10] if ICE Interface enable is not selected during reset using the boot configuration. Alternate function: PC trace status bit 0, EJTAG_PCST[0]. STI UART channel 1 data set ready. Primary function: General Purpose I/O, GPIOP[11]. At reset, this pin defaults to primary function GPIOP[11] if ICE Interface enable is not selected during reset using the boot configuration. 2nd Alternate function: PC trace status bit 1, EJTAG_PCST[1].
U1DSRN
I
U1RTSN
O
Low Drive UART channel 1 request to send. Primary function: General Purpose I/O, GPIOP[12]. At reset, this pin defaults to primary function GPIOP[12] if ICE Interface enable is not selected during reset using the boot configuration. 2nd Alternate function: PC trace status bit 2, EJTAG_PCST[2]. STI UART channel 1 clear to send. Primary function: General Purpose I/O, GPIOP[13]. At reset, this pin defaults to primary function GPIOP[13] if ICE Interface enable is not selected during reset using the boot configuration. 2nd Alternate function: PC trace clock, EJTAG_DCLK. Table 1 Pin Descriptions (Part 7 of 7)
U1CTSN
I
1. Schmitt
Trigger Input.
Boot Configuration Vector
The boot configuration vector is read into the RC32351 during cold reset. The vector defines parameters in the RC32351 that are essential to operation when cold reset is complete. The encoding of boot configuration vector is described in Table 2, and the vector input is illustrated in Figure 6.
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IDT 79RC32351
Signal MDATA[2:0]
Name/Description Clock Multiplier. This field specifies the value by which the system clock (CLKP) is multiplied internally to generate the CPU pipeline clock. 0x0 - multiply by 2 0x1 - multiply by 3 0x2 - multiply by 4 0x3 - reserved 0x4 - reserved 0x5 - reserved 0x6 - reserved 0x7 - reserved Endian. This bit specifies the endianness of RC32351. 0x0 - little endian 0x1 - big endian Reserved. Must be set to 0. Debug Boot Mode. When this bit is set, the RC32351 begins executing from address 0xFF20_0200 rather than 0xBFC0_0000 following a reset. 0x0 - regular mode (processor begins executing at 0xBFC0_0000) 0x1 - debug boot mode (processor begins executing at 0xFF20_0200) Boot Device Width. This field specifies the width of the boot device. 0x0 - 8-bit boot device width 0x1 - 16-bit boot device width 0x2 - 32-bit boot device width 0x3 - reserved EJTAG/ICE Interface Enable. When this bit is set, Alternate 2 pin functions EJTAG_PCST[2:0], EJTAG_DCLK, and EJTAG_TRST_N are selected. 0x0 - GPIOP[31, 13:10] pins behaves as GPIOP 0x1 - GPIOP[31] pin behaves as EJTAG_TRST_N, GPIOP[12:10] pins behave as EJTAG_PCST[2:0], and GPIOP[13] pin behaves as EJTAG_DCLK Fast Reset. When this bit is set, RC32351 drives RSTN for 64 clock cycles, used during test only. Clear this bit for normal operation. 0x0 - Normal reset: RC32351 drives RSTN for minimum of 4096 clock cycles 0x1 - Fast Reset: RC32351 drives RSTN for 64 clock cycles (test only) DMA Debug Enable. When this bit is set, Alternate 2 pin function, DMAP is selected. DMAP provides the DMA channel number during memory and peripheral bus DMA transactions. 0x0 - GPIOP[8, 9, 25, 23] pins behave as GPIOP 0x1 - GPIOP[8, 9, 25, 23] pins behave as DMAP[3:0] Hold SYSCLKP Constant. For systems that do not require a SYSCLKP output and can instead use CLKP, setting this bit to a one causes the SYSCLKP output to be held at a constant level. This may be used to reduce EMI. 0x0 - Allow SYSCLKP to toggle 0x1 - Hold SYSCLKP constant JTAG Boundary Scan Reset Enable. When this bit is set, Alternate 2 pin function, JTAG_TRST_N is selected. 0x0 - GPIOP[2] pin behaves as GPIOP 0x1 - GPIOP[2] pin behaves as JTAG_TRST_N CPU / DMA Transaction Indicator Enable. When this bit is set, Alternate 2 pin function, CPUP is selected. 0x0 - GPIOP[4] pin behaves as GPIOP 0x1 - GPIOP[4] pin behaves as CPUP Reserved. These pins must be driven low during boot configuration. Table 2 Boot Configuration Vector Encoding
MDATA[3]
MDATA[4] MDATA[5]
MDATA[7:6]
MDATA[8]
MDATA[9]
MDATA[10]
MDATA[11]
MDATA[12]
MDATA[13]
MDATA[15:14]
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IDT 79RC32351
Logic Diagram
The following Logic Diagram shows the primary pin functions of the RC32351.
Miscellaneous Signals
CLKP SYSCLKP COLDRSTN RSTN USBDP USBDN USBCLKP MIIRXDP[3:0] MIIRXDVP MIIRXERP MIIRXCLKP MIICRSP 4
22 32 4
MADDR[21:0] MDATA[31:0] BWEN[3:0] OEN
USB Interface
RWN 4 CSN[3:0]
BRN BGN RASN CASN SDWEN 2 SDCSN[1:0] BOEN[1:0] BDIRN SDCLKINP 12 2
Ethernet Interface
MIICOLP MIITXDP[3:0] MIITXENP MIITXERP MIITXCLKP MIIMDCP MIIMDIOP JTAG_TCK 4
RC32351 Logic
Diagram (Primary Functions)
2 10
ATMIOP[1:0] ATMOUTP[9:0]
JTAG
JTAG_TMS INSTP
JTAG_TDO
VccI/O Vss VccP (PLL) VssP (PLL) 36 GPIOP[35:0]
Figure 3 Logic Diagram
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General Purpose Input/Output May 25, 2004
Power/Ground
VccCore
Debug
JTAG_TDI
ATM Interface
ATMINP[11:0]
Memory and Peripheral Bus
WAITACKN
IDT 79RC32351
Clock Parameters
(Ta = 0C to +70C Commercial, Vcc I/O = +3.3V5%, Vcc Core and VccP = +2.5V5%)
RC32351 100MHz Min 100 25 20 10 10 -- -- -- Max 100 50 40 -- -- 3 3 250 RC32351 133MHz Min 100 25 15 6 6 -- -- -- Max 133 67 40 -- -- 3 3 250 MHz MHz ns ns ns ns ns ps Timing Diagram Reference Figure 4
Parameter Internal CPU pipeline clock CLKP2,3,4
1
Symbol Frequency Frequency Tperiod1 Thigh1 Tlow1 Trise1 Tfall1 Tjitter
Reference Edge none none
Units
1 The CPU pipeline clock speed is selected during cold reset by the boot configuration vector (see Table 2). 3 USB clock (USBCLKP) frequency must be less than CLKP frequency.
2 Ethernet clock (MIIRXCLKP and MIITXCLKP) frequency must be equal to or less than 1/2 CLKP frequency. 4 ATM Utopia clock (RXCLKP and TXCLKP) frequency must be equal to or less than 1/2 CLKP frequency.
Table 3 Clock Parameters
Tlow1 Tperiod1 CLKP Tjitter Tjitter Trise1 Tfall1 Thigh1
Figure 4 Clock Parameters Waveform
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IDT 79RC32351
AC Timing Definitions
Below are examples of the AC timing characteristics used throughout this document.
Tlow Tperiod clock Tdo Output signal 1 Tzd Output signal 2 Tsu Input Signal 1 Tpw Signal Thld Tdz Tdo Tjitter Trise Tfall Thigh
Figure 5 AC Timing Definitions Waveform
Symbol Tperiod Tlow Thigh Trise Tfall Tjitter Tdo Tzd Tdz Tsu Thld Tpw Clock period. Clock low. Amount of time the clock is low in one clock period.
Definition
Clock high. Amount of time the clock is high in one clock period. Rise time. Low to high transition time. Fall time. High to low transition time. Jitter. Amount of time the reference clock (or signal) edge can vary on either the rising or falling edges. Data out. Amount of time after the reference clock edge that the output will become valid. The minimum time represents the data output hold. The maximum time represents the earliest time the designer can use the data. Z state to data valid. Amount of time after the reference clock edge that the tri-stated output takes to become valid. Data valid to Z state. Amount of time after the reference clock edge that the valid output takes to become tri-stated. Input set-up. Amount of time before the reference clock edge that the input must be valid. Input hold. Amount of time after the reference clock edge that the input must remain valid. Pulse width. Amount of time the input or output is active. Table 4 AC Timing Definitions
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IDT 79RC32351
AC Timing Characteristics
(Ta = 0C to +70C Commercial, Vcc I/O = +3.3V5%,Vcc Core = +2.5V5%, VccP = +2.5V5%)
Signal Reset and System COLDRSTN
1
Symbol
Reference Edge
100MHz Min Max
133MHz Min Max
Unit
Conditions
Timing Diagram Reference
Tpw1 Trise1
none none CLKP rising COLDRSTN rising CLKP rising CLKP rising CLKP rising none none CLKP rising CLKP rising
110 -- 4.0 3 5 3.5 3.5 (CLKP+7) (CLKP+7) 3.5 1.6 0
-- 5.0 10.7 -- 8 7 6.6 -- -- 5.9 -- -- 5.8
110 -- 4.0 3 5.0 3.5 3.5 (CLKP+7) (CLKP+7) 3.5 1.6 0 3.3
-- 5.0 10.7 -- 8.0 7.0 6.6 -- -- 5.9 -- -- 5.8
ms ns ns ns ns ns ns ns ns ns ns ns ns
Figure 6 Figure 7
RSTN
Tdo2 Thld3 Tdo Tdo Tdo Tpw Tpw Tdo Tsu Thld
MDATA[15:0] Boot Configuration Vector INSTP CPUP DMAP DMAREQN2 DMADONEN2 DMAFIN BRN
BGN
Tdo
CLKP rising
3.3
1 RSTN is a bidirectional signal. It is treated as an asynchronous input.
2 DMAREQN and DMADONEN minimum pulse width equals the CLKP period plus 7ns.
Table 5 Reset and System AC Timing Characteristics
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IDT 79RC32351
1
2
3
4
5
6
7
8
CLKP
SYSCLKP
Trise1
COLDRSTN
Tdo2
RSTN
Thld3
BOOT VECT
MDATA[31:0]
FFFF_FFFF
BDIRN
BOEN[0]
>= 100 ms Tpw1
>=10ms
>= 4096 CLKP clock cycles OR >= 64 CLKP clock cycles *
>= 4096 CLKP clock cycles OR >= 64 CLKP clock cycles *
* Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).
1. 2. 3. 4. 5. 6. 7. 8. COLDRSTN asserted by external logic. The RC32351 asserts RSTN, asserts BOEN[0] low, drives BDIRN low, and tri-states the data bus in response. External logic begins driving valid boot configuration vector on the data bus, and the RC32351 starts sampling it. External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be tri-stated before COLDRSTN is deasserted. The RC32351 stops sampling the boot configuration vector. The RC32351 starts driving the data bus, MDATA[31:0], deasserts BOEN[0] high, and drives BDIRN high. SYSCLKP may be held constant after this point if Hold SYSCLKP Constant is selected in the boot configuration vector. RSTN negated by RC32351. CPU begins executing by taking MIPS reset exception, and the RC32351 starts sampling RSTN as a warm reset input. Figure 6 Cold Reset AC Timing Waveform
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IDT 79RC32351
1
2
3
4
5
CLKP
COLDRSTN
RSTN FFFF_FFFF
MDATA[31:0] Active Deasserted
Mem Control Signals
Active
>= 4096 CLKP clock cycles OR >= 64 CLKP clock cycles*
>= 4096 CLKP clock cycles OR >= 64 CLKP clock cycles* (RSTN ignored during this period to allow pull-up to drive signal high)
* Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).
1. 2. 3. 4. 5. Warm reset condition caused by either RSTN asserted, write to reset register, or bus transaction timer time-out. The RC32351 asserts RSTN output low in response. The RC32351 tri-states the data bus, MDATA[31:0], and deasserts all memory control signals, such as RASN, CASN, RWN, OEN, etc. The RC32351 deasserts RSTN. The RC32351 starts driving the data bus, MDATA[31:0], again, but does not sample the RSTN input. CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again. Figure 7 Warm Reset AC Timing Waveform
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IDT 79RC32351 100MHz Reference Edge Min Max 133MHz Min Max Timing Diagram Reference
Signal
Symbol
Unit
Conditions
Memory and Peripheral Bus - SDRAM Access MDATA[31:0] Tsu1 Thld1 Tdo1 Tdz1 Tzd1 MADDR[20:2], BWEN[3:0] CASN, RASN, SDCSN[1:0], SDWEN CKENP BDIRN BOEN[1:0] SYSCLKP rising SDCLKINP Tdo2 Tdo3 Tdo4 Tdo5 Tdo6 Tdo7 Tperiod8 Thigh8,Tlow8 Trise8,Tfall8 Tdelay8 SYSCLKP rising SYSCLKP rising SYSCLKP rising SYSCLKP rising SYSCLKP rising SYSCLKP rising CLKP rising none SDCLKINP rising SYSCLKP rising 2.5 1.2 1.2 -- 1.0 1.2 1.2 1.2 1.2 1.2 0.5 20 10 -- 0 -- -- 5.8 5.0 -- 5.3 5.3 5.3 5.3 5.3 5.0 50 -- 3.0 4.8 2.5 1.2 1.2 -- 1.0 1.2 1.2 1.2 1.2 1.2 0.5 15 6.0 -- 0 -- -- 5.8 5.0 -- 5.3 5.3 5.3 5.3 5.3 5.0 50 -- 3.0 4.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 8 Figure 9 Figure 10
Table 6 Memory and Peripheral Bus AC Timing Characteristics (Part 1 of 2)
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IDT 79RC32351 100MHz Reference Edge Min Max 133MHz Min Max Timing Diagram Reference
Signal
Symbol
Unit
Conditions
Memory and Peripheral Bus - Device Access MDATA[31:0] Tsu1 Thld1 Tdo1 Tdz1 Tzd1 WAITACKN, BRN Tsu Thld MADDR[21:0] Tdo2 Tdz2 Tzd2 MADDR[25:22] Tdo3 Tdz3 Tzd3 BDIRN, BOEN[0] Tdo4 Tdz4 Tzd4 BGN, BWEN[3:0], OEN, RWN Tdo5 Tdz5 Tzd5 CSN[3:0] Tdo6 Tdz6 Tzd6 CSN[5:4] Tdo7 Tdz7 Tzd7 CLKP rising CLKP rising CLKP rising CLKP rising CLKP rising CLKP rising CLKP rising CLKP rising 2.5 1.5 2.0 -- 2.0 2.5 1.5 2.0 -- 2.0 2.5 -- 2.0 2.0 -- 2.0 2.0 -- 2.0 1.7 -- 2.0 2.5 -- 2.0 -- -- 6.5 9.0 -- -- -- 6.0 9.0 -- 6.5 9.0 -- 6.0 9.0 -- 6.0 9.0 -- 5.0 9.0 -- 6.0 9.0 -- 2.5 1.5 2.0 -- 2.0 2.5 1.5 2.0 -- 2.0 2.5 -- 2.0 2.0 -- 2.0 2.0 -- 2.0 1.7 -- 2.0 2.5 -- 2.0 -- -- 6.5 9.0 -- -- -- 6.0 9.0 -- 6.5 9.0 -- 6.0 9.0 -- 6.0 9.0 -- 5.0 9.0 -- 6.0 9.0 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 11 Figure 12
Table 6 Memory and Peripheral Bus AC Timing Characteristics (Part 2 of 2)
Note: The RC32351 provides bus turnaround cycles to prevent bus contention when going from a read to write, write to read, and during external bus ownership. For example, there are no cycles where an external device and the RC32351 are both driving. See Chapter 10, "Device Controller," Chapter 11, "Synchronous DRAM Controller," and Chapter 12, "Bus Arbitration" in the RC32351 User Reference Manual.
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IDT 79RC32351
CLKP Tdo7 SYSCLKP
SDRAM CAS Latency
Tdo2 MADDR[21:0] Addr Tdo2 BWEN[3:0] 1111 BE's Tdo3 CMD[2:0]* NOP READ Tdo3 SDCSN[1:0] 11 Chip-Sel Tdo5 BDIRN Tdo6 BOEN[1:0] 11 Tdz1 MDATA[31:0] Data RC32351 samples read data SDCLKINP Buffer Enables Tsu1 Thld1 Tdo6 11 Tdo5 NOP 1111
Tdelay8
11 Tzd1
* NOTE: CMD[2:0] = {RASN, CASN, SDWEN}
Figure 8 Memory and Peripheral Bus AC Timing Waveform - SDRAM Read Access
Vcc SYSCLKP
Tdelay8
pull-up RSTN COLDRSTN CLKP
RC32351
SDCLKINP
Memory Bus external buffer
SDRAM
SRAM, EPROM, etc.
Figure 9 SYSCLKP - SDCLKINP Relationship
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IDT 79RC32351
CLKP Tdo7 SYSCLKP Tdo2 MADDR[21:0] Tdo2 BWEN[3:0] 1111 Tdo3 CMD[2:0]* NOP Tdo3 SDCSN[1:0] 11 Chip-Sel Tdo5 BDIRN Tdo6 BOEN[1:0] 11 Buff Enable Tdo1 MDATA[31:0] Data 11 11 WRITE NOP BE's 1111 Addr
SDRAM samples write data
* NOTE: CMD[2:0] = {RASN, CASN, SDWEN}
Figure 10 Memory and Peripheral Bus AC Timing Waveform - SDRAM Write Access
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IDT 79RC32351
CLKP Tdo2 MADDR[21:0] Tdo3 MADDR[25:22] RWN Tdo6 Tdo6 CSN[3:0] Addr[25:22] Addr[21:0]
BWEN[3:0] Tdo5 OEN
1111 Tdo5
Thld1 Tdz1 MDATA[31:0] Tdo4 BDIRN Tdo4 BOEN[0] WAITACKN
RC32351 samples read data
Tsu1 Data
Tzd1
Tdo4
Tdo4
Figure 11 Memory and Peripheral Bus AC Timing Waveform - Device Read Access
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IDT 79RC32351
CLKP Tdo2 MADDR[21:0] Tdo3 MADDR[25:22] Tdo5 RWN Tdo6 CSNx Tdo5 BWEN[3:0] OEN Tdo1 MDATA[31:0] BDIRN Tdo4 BOEN[0] WAITACKN Data 1111 Byte Enables 1111 Addr[25:22] Addr[21:0]
Figure 12 Memory AC and Peripheral Bus Timing Waveform - Device Write Access
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IDT 79RC32351 100MHz Min Max 133MHz Min Max Timing Diagram Reference
Signal Ethernet1,2 MIIRXCLKP, MIITXCLKP
Symbol
Reference Edge
Unit
Conditions
Tperiod1 Thigh1,Tlow1 Trise1,Tfall1
none
399.96 400.04 399.96 400.04 140 -- 260 3 140 -- 260 3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10 Mbps
Figure 13
MIIRXCLKP, MIITXCLKP
Tperiod1 Thigh1,Tlow1 Trise1,Tfall1
none
39.996 40.004 39.996 40.004 14 -- 26 2 -- -- 13 -- -- 11 8 -- -- 7 14 -- 5 3 7 30 14 -- -- 6 0.5 3 26 2 -- -- 13 -- -- 11 8 -- -- 7
100 Mbps
MIIRXDP[3:0], MIIRXDVP, MIIRXERP MIITXDP[3:0], MIITXENP, MIITXERP MIIMDCP
Tsu2 Thld2 Tdo3 Tperiod4 Thigh4,Tlow4 Trise4 Tfall4
MIIRXCLKP rising MIITXCLKP rising none
5 3 7 30 14 -- --
MIIMDIOP
Tsu5 Thld5 Tdo5
MIIMDCP rising
6 0.5 3
1 Ethernet clock (MIIRXCLKP and MIITXCLKP) frequency must be equal to or less than 1/2 CLKP frequency. 2 MIICOLP and MIICRSP are asynchronous signals.
Table 7 Ethernet AC Timing Characteristics
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IDT 79RC32351
Thigh1 Tperiod1 MIIRXCLKP Thld2 Tsu2 MIIRXDVP, MIIRXDP[3:0], MIIRXERP Thigh1 Tperiod1 MIITXCLKP Tdo3 Tdo3 MIITXENP, MIITXDP[3:0], MMTXERP Thigh4 Tperiod4 MIIMDCP Tdo5 MIIMDIOP (output) Thld5 Tsu5 MIIMDIOP (input)
Tlow1
Tlow1
Tlow4
Tdo5
Figure 13 Ethernet AC Timing Waveform
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IDT 79RC32351 100MHz Reference Edge Min Max 133MHz Min Max Timing Diagram Reference
Signal
Symbol
Unit
Conditions
ATM Interface, Utopia Mode1,2 RXCLKP, TXCLKP1 Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 RXCLKP, TXCLKP1 Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 RXCLKP, TXCLKP Tperiod1 Thigh,Tlow1 Trise1,Tfall1 TXFULLN Tsu2 Thld2 TXDATA[7:0], TXSOC, TXENBN, TXADDR[1:0] RXDATA[7:0], RXEMPTYN, RXSOC RXADDR[1:0], RXENBN Tdo3 Tsu4 Thld4 Tdo5 TXCLKP rising TXCLKP rising RXCLKP rising RXCLKP rising none none none -- 16 -- -- 12 -- -- 8 -- 2 2 4 3 2 3 40 -- 4 30 -- 3 20 -- 2 -- -- 8 -- -- 8 -- 16 -- -- 12 -- -- 8 -- 2 2 4 3 2 3 40 -- 4 30 -- 3 20 -- 2 -- -- 8 -- -- 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 50 MHz Utopia 33 MHz Utopia 25 MHz Utopia Figure 14
Table 8 ATM AC Timing Characteristics
1.
ATM Utopia clock (RXCLKP and TXCLKP) frequency must be equal to or less than 1/2 CLKP frequency. Utopia Mode pins are multiplexed on the ATM interface pins as described in Table 9.
2. All
Tperiod1 TXCLKP Tsu2 TXFULL Tdo3 TXDATA,TXSOC,TXENB,TXADDR Tperiod1 RXCLKP Tsu4 RXDATA, RXEMPTY, RXSOC Tdo5 RXADDR, RXENB Thld4 Thld2
Figure 14 ATM AC Timing Waveform
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IDT 79RC32351
ATM Pin Name ATMINP[0] ATMINP[1] ATMINP[2] ATMINP[3] ATMINP[4] ATMINP[5] ATMINP[6] ATMINP[7] ATMINP[8] ATMINP[9] ATMINP[10] ATMINP[11] ATMIOP[0] ATMIOP[1] ATMOUTP[0] ATMOUTP[1] ATMOUTP[2] ATMOUTP[3] ATMOUTP[4] ATMOUTP[5] ATMOUTP[6] ATMOUTP[7] ATMOUTP[8] ATMOUTP[9] GPIOP[22] GPIOP[23] GPIOP[24] GPIOP[25]
Utopia Level 1 RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXCLKP RXEMPTYN RXSOC TXFULLN RXENBN TXCLKP TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXSOC TXENBN
Utopia Level 2 RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXCLKP RXEMPTYN RXSOC TXFULLN RXENBN TXCLKP TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXSOC TXENBN TXADDR[0] TXADDR[1] RXADDR[0] RXADDR[1]
Table 9 ATM I/O Pin Description
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IDT 79RC32351 100MHz Reference Edge Min Max 133MHz Min Max Timing Diagram Reference
Signal USB USBCLKP1
Symbol
Unit
Conditions
Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 Tjitter1
none
19.79 21.87 19.79 21.87 8.3 -- -- 4 -- 3 0.8 20 8.3 -- -- 4 -- 3 0.8 20
ns ns ns ns ns 1/4th of the minimum Source data jitter Universal Serial Bus Specification (USBS) Revision 1.1: Figures 7.6 and 7.7. USBS Revision 1.1: Figures 7.6 and 7.7. USBS Revision 1.1: Note 10, Section 7.1.2.
Figure 15
USBDN, USBDP
Trise2
Tfall2 USBDN and USBDP Rise and Fall Time Matching Data valid period Skew between USBDN and USBDP Source data jitter Receive data jitter Source EOP length Receive EOP length EOP jitter Full-speed Data Rate Frame Interval Consecutive Frame Interval Jitter Tfdrate Tseop Treop Tstate
4 90
20 111.11
4 90
20 111.11
ns %
60 -- -- -- 160 82 -2
-- 0.4 3.5 12 175 -- 5
60 -- -- -- 160 82 -2
-- 0.4 3.5 12 175 -- 5
ns ns ns ns ns ns ns MHz ms ns ns Average bit rate, USBS Section 7.1.11. USBS Section 7.1.12. Without frame adjustment. With frame adjustment. USBS Revision 1.1: Section 7.1.3 USBS Revision 1.1: Table 7-6
11.97 12.03 11.97 12.03 0.9995 1.0005 0.9995 1.0005 -- -- 42 126 -- -- 42 126
1
USB clock (USBCLKP) frequency must be less than CLKP frequency. Table 10 USB AC Timing Characteristics
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Tfall1
USBCLKP Tjitter1 USBDN 90% Tperiod1 Thigh1 90% Trise1 Tstate Tlow1
USBDP
10% Trise2 Tfdrate Tfall2
10%
USBDN
USBDP Tseop Treop
Figure 15 USB AC Timing Waveform
Signal UART U0SINP, U0RIN, U0DCDN, U0DSRN, U0CTSN, U1SINP, U1DSRN, U1CTSN U0SOUTP, U0DTRN, U0RTSN, U1SOUTP, U1DTRN, U1RTSN
Symbol
100MHz Reference Edge Min Max
133MHz Min Max
Unit
Conditions
Timing Diagram Reference
Tsu1 Thld1 Tdo1
CLKP rising
5 3
-- --
ns ns
CLKP rising
1
12
ns
1 These are asynchronous signals and the values are provided for ATE (test) only.
Table 11 UART AC Timing Characteristics
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IDT 79RC32351 100MHz Reference Edge Min Max 133MHz Min Max Timing Diagram Reference
Signal GPIOP GPIOP[31:0]1
Symbol
Unit
Conditions
Tsu1 Thld1 Tdo1
CLKP rising
4 1.4 2 3 1 3
-- -- 8 -- -- 8
4 1.4 2 3 1 3
-- -- 8 -- -- 8
ns ns ns ns ns ns
Figure 16
GPIOP[35:32]2
Tsu1 Thld1 Tdo1
1 2
GPIO[31:0] can be asynchronous signals; the values are provided for ATE (test) only. GPIOP[35:32] are synchronous signals. Table 12 GPIOP AC Timing Characteristics
CLKP Tdo1 GPIOP (output) Thld1 Tsu1 GPIOP (input) Tdo1
Figure 16 GPIOP AC Timing Waveform
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IDT 79RC32351 100MHz Min Max 133MHz Min Max Timing Diagram Reference
Signal EJTAG and JTAG JTAG_TCK
Symbol
Reference Edge
Unit
Conditions
Tperiod1 Thigh1,Tlow1 Trise1,Tfall1
1
none
100 40 --
-- -- 5 10.0 -- 3.5 -- -- 12.0 1.0 -- -- 3.3
100 40 -- 7.5 2.5 -- 3.0 1.0 2.0 -0.72 100 2 -0.32
-- -- 5 10.0 -- 3.5 -- -- 12.0 1.0 -- -- 3.3
ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 17
EJTAG_DCLK
Tperiod2 Thigh2,Tlow2 Trise2,Tfall2
none
10.0 2.5 --
JTAG_TMS, JTAG_TDI, JTAG_TRST_N JTAG_TDO
Tsu3 Thld3 Tdo4 Tdo5
JTAG_TCK rising
3.0 1.0
JTAG_TCK falling
2.0
EJTAG_DCLK rising -0.72 none JTAG_TCK rising 100 2
JTAG_TRST_N
Tpw6 Tsu6
EJTAG_PCST[2:0]
1. EJTAG_DCLK 2.
Tdo7
EJTAG_DCLK rising -0.32
is equal to the internal CPU pipeline clock.
A negative delay denotes the amount of time before the reference clock edge.
Table 13 JTAG AC Timing Characteristics Tperiod1 JTAG_TCK Trise1 EJTAG_DCLK Tlow1 Tfall1 Thigh1 Thigh2 Trise2 JTAG_TMS, JTAG_TDI Tsu3 JTAG_TDO TDO Tdo4 EJTAG_PCST Tdo7 JTAG_TRST_N EJTAG_TRST_N Tpw6 Figure 17 JTAG AC Timing Waveform Thld3 TDO Tdo5 PCST TPC Tfall2 EJTAG TPC, TCST capture
Tperiod2 Tlow2
Tsu6
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Table 14 shows the pin numbering for the Standard EJTAG connector. All the even numbered pins are connected to ground. Multiplexing of pin functions should be considered when connecting EJTAG_TRST_N and EJTAG_PCST. For details on using the JTAG connector, see the JTAG chapters in the RC32351 user reference manual.
PIN 1 SIGNAL EJTAG_TRST_N RC32351 I/O Input TERMINATION1 10 k pull-down resistor. A pull-down resistor will hold the EJTAG controller in reset when not in use if the EJTAG_TRST_N function is selected with the boot configuration vector. Refer to the User Manual. 10 k pull-up resistor 33 series resistor 10 k pull-up resistor 10 k pull-up resistor2 10 k pull-up resistor is used if it is combined with the system cold reset control, COLDRSTN. 33 series resistor 33 series resistor 33 series resistor 33 series resistor This can be connected to the boot configuration vector to control debug boot mode if desired. Refer to Table 2 on page 12 and the RC32351 user reference manual. Used to sense the circuit board power. Must be connected to the VCC I/O supply of the circuit board.
3 5 7 9 11 13 15 17 19 21 23
1. 2.
JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK System Reset EJTAG_PCST[0] EJTAG_PCST[1] EJTAG_PCST[2] EJTAG_DCLK Debug Boot VCCI/O
Input Output Input Input Input Output Output Output Output Input Output
Table 14 Pin Numbering of the JTAG and EJTAG Target Connector
The value of the series resistor may depend on the actual printed circuit board layout situation. JTAG_TCK pull-up resistor is not required according to the JTAG (IEEE1149) standard. It is indicated here to prevent a floating CMOS input when the EJTAG connector is unconnected.
Output Loading for AC Timing
1.5V
50 RC32351 Output
.
50
Test Point
Signal All High Drive Signals All Low Drive Signals
1.
Equivalent Lump Capacitance 50 pF1 25 pF
An equivalent load of 50 pF is derived from the tester load plus an external load.
Figure 18 Output Loading for AC Timing
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Phase-Locked Loop (PLL)
The processor aligns the pipeline clock, PClock, to the master input clock (CLKP) by using an internal phase-locked loop (PLL) circuit that generates aligned clocks. Inherently, PLL circuits are only capable of generating aligned clocks for master input clock (CLKP) frequencies within a limited range. PLL Analog Filter The storage capacitor required for the Phase-Locked Loop circuit is contained in the RC32351. However, it is recommended that the system designer provide a filter network of passive components for the PLL power supply. VCCP (PLL circuit power) and VSSP (PLL circuit ground) should be isolated from VCC Core (core power) and VSS (common ground) with a filter circuit such as the one shown in Figure 19. Because the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further experimentation within your specific application.
10 ohm1 Vcc 10 F Vss
1.
RC32351
VccP 0.1 F 100 pF VssP
This resistor may be required in noisy circuit environments. Figure 19 PLL Filter Circuit for Noisy Environments
Recommended Operating Temperature and Supply Voltage
Grade Commercial
2
Temperature 0C to +70C Ambient
Vss1 VssP5 0V
VccI/O2 3.3V5%
VccCore3 VccP4 2.5V5%
1 Vss supplies a common ground. 3 VccCore is the internal logic power. 4 VccP is the phase lock loop power. 5
VccI/O is the I/O power.
VssP is the phase lock loop ground. Table 15 Temperature and Voltage
Capacitive Load Deration
Refer to the RC32355 IBIS Model which can be found at the IDT web site (www.idt.com).
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Power-on RampUp
The 2.5V core supply (and 2.5V VccPLL supply) can be fully powered without the 3.3V I/O supply. However, the 3.3V I/O supply cannot exceed the 2.5V core supply by more than 1 volt during power up. A sustained large power difference could potentially damage the part. Inputs should not be driven until the part is fully powered. Specifically, the input high voltages should not be applied until the 3.3V I/O supply is powered. There is no special requirement for how fast Vcc I/O ramps up to 3.3V. However, all timing references are based on a stable Vcc I/O.
DC Electrical Characteristics
(Tambient = 0C to +70C Commercial, Vcc I/O = +3.3V5%, Vcc Core and Vcc P = +2.5V5%)
Parameter LOW Drive Output with Schmitt Trigger Input (STI) IOL IOH VIL VIH VOH HIGH Drive Output with Standard Input IOL IOH VIL VIH VOH Clock Drive Output Capacitance Leakage IOL IOH CIN I/OLEAK Min 7.3 -8.0 -- 2.0 Vcc - 0.4 9.4 -15 -- 2.0 Vcc - 0.4 39 -24 -- -- Max -- -- 0.8 Unit mA mA V V V mA mA V V V mA mA pF All pins All pins 183 49,51,54,55,106-108,110,112-117,119, 121,123-128,130,132-137,139,141,143, 150,152,154-159,161,163-166,168-170, 172,174-179,181,185-190,192,194-200, 202,204 Pin Numbers Conditions
1-4,6-8,10-16,18,20-25,27-29,32,33,35-37, VOL = 0.4V 39-42,44,46-48,50,52,53,56,58-60,62-69, VOH = (Vcc I/O - 0.4) 71-77,82-85,87-94,96-99,101-105,167, 205-208 -- -- -- VOL = 0.4V VOH = (Vcc I/O - 0.4) -- -- -- VOL = 0.4V VOH = (Vcc I/O - 0.4) -- --
(VccI/O
+ 0.5) -- -- -- 0.8
(VccI/O
+ 0.5) -- -- -- 10 20
A
Table 16 DC Electrical Characteristics
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USB Electrical Characteristics
Parameter USB Interface Vdi Vcm Vse Cin Ili Voh Vol Zo Differential Input Sensitivity Differential Input Common Mode Range Single ended Receiver Threshold Transceiver Capacitance Hi-Z State Data Line Leakage -10 -0.2 0.8 0.8 2.5 2.0 20 10 V V V pF s V V Including Rext = 20 0V < Vin < 3.3V 15km + 5% to Gnd[7] I(D+)-(D-)I Min Max Unit Conditions
USB Upstream/Downstream Port Static Output High Static Output Low USB Driver Output Impedance 28 2.8 3.6 0.3 44
Table 17 USB Interface Characteristics
Power Consumption
Note: This table is based on a 2:1 CPU bus (PClock to CLKP) clock ratio.
Parameter 100MHz Typical ICC I/O ICC core Power Dissipation Normal mode Standby mode Normal mode Standby mode1
1
133MHz Typical 80 400 320 1.26 1.06 Max. 130 450 370 1.63 1.42
Unit
Max. 110 350 290 1.30 1.09
Conditions
60 300 240 0.95 0.80
mA mA mA W W CL = 0 Ta = 25oC VccP = 2.625V (for max. values) Vcc core = 2.625V (for max. values) Vcc I/O = 3.46V (for max. values) VccP = 2.5V (for typical values) Vcc core = 2.5V (for typical values) Vcc I/O = 3.3V (for typical values)
1. RISCore 32300 CPU core enters Standby mode by executing WAIT instructions; however, other logic continues to function. Standby mode reduces power consumption by 0.6 mA per MHz of the CPU pipeline clock, PClock.
Table 18 RC32351 Power Consumption
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Power Curve
The following graph contains a power curve that shows power consumption at various bus frequencies. Note: The system clock (CLKP) can be multiplied by 2, 3, or 4 to obtain the CPU pipeline clock (PClock) speed.
Typical Power Curve
2.0 Power (W @ 3.3v IO & 2.5v core) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 25 30 35 40 45 50 55 60 65 System Bus Speed (MHz) 2x
Figure 20 Typical Power Usage
Absolute Maximum Ratings
Symbol VCCI/O VCCCore VCCP Vimin Vi Ta, Commercial Tstg
1.
Parameter I/O Supply Voltage Core Supply Voltage PLL Supply Voltage Input Voltage - undershoot I/O Input Voltage Ambient Operating Temperature Storage Temperature
Min1 -0.3 -0.3 -0.3 -0.6 Gnd 0 -40
Max1 4.0 3.0 3.0 -- VCCI/O+0.5 70 125
Unit V V V V V degrees C degrees C
Table 19 Absolute Maximum Ratings
Functional and tested operating conditions are given in Table 15. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
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Package Pin-out -- 208-Pin PQFP
The following table lists the pin numbers and signal names for the RC32351.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Function ATMOUTP[0] ATMOUTP[1] ATMINP[02] ATMOUTP[2] Vss ATMOUTP[3] ATMINP[03] ATMOUTP[4] Vcc I/O ATMOUTP[5] ATMINP[04] ATMOUTP[6] ATMOUTP[7] ATMINP[05] ATMOUTP[8] ATMOUTP[9] Vss ATMINP[06] Vcc Core GPIOP[00] GPIOP[01] ATMINP[07] GPIOP[02] GPIOP[03] ATMINP[08] Vcc I/O GPIOP[04] GPIOP[05] ATMINP[09] VccP1 VssP
1
Alt
Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
Function JTAG_TDO GPIOP[16] GPIOP[17] GPIOP[18] Vss JTAG_TCK GPIOP[19] GPIOP[20] Vcc I/O GPIOP[21] JTAG_TDI GPIOP[22] GPIOP[23] GPIOP[24] JTAG_TMS GPIOP[25] GPIOP[26] Vss GPIOP[27] COLDRSTN GPIOP[28] GPIOP[29] GPIOP[30] GPIOP[31] USBCLKP Vcc I/O USBDN USBDP Vss MIICRSP MIICOLP MIITXDP[0] MIITXDP[1] Vcc Core MIITXDP[2] MIITXDP[3] MIITXENP
Alt
Pin 105
Function BGN CSN[0] CSN[1] CSN[2] Vcc I/O CSN[3] Vss OEN RWN BDIRN BOEN[0] BOEN[1] BWEN[0] Vcc I/O BWEN[1] Vss BWEN[2] Vcc Core BWEN[3] MDATA[00] MDATA[16] MDATA[01] MDATA[17] MDATA[02] Vcc I/O MDATA[18] Vss MDATA[03] MDATA[19] MDATA[04] MDATA[20] MDATA[05] MDATA[21] Vcc Core MDATA[06] Vcc I/O MDATA[22]
Alt
Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193
Function MDATA[28] MDATA[13] MDATA[29] Vcc I/O MDATA[14] Vss MDATA[30] MDATA[15] MDATA[31] CLKP WAITACKN MADDR[00] MADDR[11] MADDR[01] Vcc I/O MADDR[12] Vss MADDR[02] MADDR[13] MADDR[03] MADDR[14] MADDR[04] MADDR[15] Vcc I/O MADDR[05] Vcc Core SYSCLKP Vss MADDR[16] MADDR[06] MADDR[17] MADDR[07] MADDR[18] MADDR[08] Vcc I/O MADDR[19] Vss
Alt
1 1 1
106 107 108 109 110
1 1 1 1 2 1 2
111 112 113 114 115 116 117 118 119 120 121 122
1 1 1 1 2
123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141
1 1 2 1
72 73 74 75 76 77 78
2 1
79 80 81 82 83 84
ATMINP[10] GPIOP[06] Vss GPIOP[07] ATMINP [11] GPIOP[08] 2 1 1
85 86 87 88 89
Table 20: 208-pin QFP Package Pin-Out (Part 1 of 2)
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IDT 79RC32351 Pin 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Function Vcc Core GPIOP[09] GPIOP[10] GPIOP[11] GPIOP[12] Vcc I/O GPIOP[13] Vss GPIOP[14] GPIOP[15] GPIOP[35] GPIOP[34] GPIOP[33] GPIOP[32] INSTP 2 2 2 2 2 Alt Pin 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Function MIITXCLKP MIITXERP MIIRXERP MIIRXCLKP MIIRXDVP Vcc I/O MIIRXDP[0] MIIRXDP[1] MIIRXDP[2] MIIRXDP[3] Vss MIIDCP MIIDIOP RSTN BRN Alt Pin 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Function Vss MDATA[07] MDATA[23] SDCLKINP MDATA[08] MDATA[24] MDATA[09] MDATA[25] MDATA[10] Vcc I/O MDATA[26] Vss MDATA[11] MDATA[27] MDATA[12] Alt Pin 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function MADDR[09] MADDR[20] MADDR[10] MADDR[21] CASN RASN SDWEN Vcc I/O SDCSN[0] Vss SDCSN[1] ATMINP[00] ATMIOP[0] ATMIOP[1] ATMINP[01] Alt
1 VccP and VssP are the Phase Lock Loop (PLL) power and ground. PLL power and ground should be supplied through a special filter circuit.
Table 20: 208-pin QFP Package Pin-Out (Part 2 of 2)
Alternate Pin Functions
Pin 20 21 23 24 27 28 33 35 37 39 40 41 42 44 54 Primary GPIOP[00] GPIOP[01] GPIOP[02] GPIOP[03] GPIOP[04] GPIOP[05] GPIOP[06] GPIOP[07] GPIOP[08] GPIOP[09] GPIOP[10] GPIOP[11] GPIOP[12] GPIOP[13] GPIOP[16] Alt #1 U0SOUTP U0SINP U0RIN U0DCRN U0DTRN U0DSRN U0RTSN U0CTSN U1SOUTP U1SINP U1DTRN U1DSRN U1RTSN U1CTSN CSN[4] Table 21 Alternate Pin Functions DMAP[3] DMAP[2] EJTAG_PCST[0] EJTAG_PCST[1] EJTAG_PCST[2] EJTAG_DCLK CPUP JTAG_TRST_N Alt #2 Pin 55 56 59 60 62 64 65 66 68 71 73 74 75 76 Primary GPIOP[17] GPIOP[18] GPIOP[19] GPIOP[20] GPIOP[21] GPIOP[22] GPIOP[23] GPIOP[24] GPIOP[25] GPIOP[27] GPIOP[28] GPIOP[29] GPIOP[30] GPIOP[31] Alt #1 CSN[5] DMAREQN DMADONEN USBSOF CKENP TXADDR[0] TXADDR[1] RXADDR[0] RXADDR[1] MADDR[22] MADDR[23] MADDR[24] MADDR[25] DMAFIN EJTAG_TRST_N DMAP[1] DMAP[0] Alt #2
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IDT 79RC32351
Package Drawing - 208-pin QFP
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Package Drawing - page two
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IDT 79RC32351
Ordering Information
79RCXX Product Type YY Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process
Blank
Commercial Temperature (0C to +70C Ambient)
DH 100 133
208-pin QFP 100 MHz Pipeline Clk 133 MHz Pipeline Clk
351
Integrated Core Processor
T 79RC32
2.5V +/-5% Core Voltage 32-bit Embedded Microprocessor
Valid Combinations
79RC32T351 -100DH 79RC32T351 -133DH 208-pin QFP package, Commercial Temperature 208-pin QFP package, Commercial Temperature
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
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for Tech Support: email: rischelp@idt.com phone: 408-284-8208
May 25, 2004

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